MicroNanoSystems News
Nano control of variability
SCIENTISTS at the University of the continued scaling of technology to tackle the problem in the
Glasgow, in collaboration with Complementary Metal-oxide framework of NanoCMOS, funded by
colleagues from Edinburgh, Manchester, Semiconductor (CMOS) microchips in the EPSRC, in collaboration with
Southampton and York universities, future nano-scale technology leading design houses, chip
have developed technology which will generations. Professor Asen Asenov, manufacturers and software vendors.
help microchip designers create future who is the principal investigator of Using grid computing technology,
integrated circuits. As part of a £5.3m NanoCMOS and leads the device simulations of huge numbers of
Engineering and Physical Sciences modelling team at Glasgow which microscopically different nano-transistos
Research Council (EPSRC) eScience developed the simulation tools, said: have been carried out on thousands of
pilot project called NanoCMOS they “Nano-scale transistors are at the heart microprocessors on networked
have developed simulation tools which of our computers, mobile phones, cars, computer clusters consuming more than
take advantage of grid computing to TV sets and games consoles chips. They 20 years’ of CPU time in a week. As a
predict how billions of nano-transistors, play a crucial role in the UK vision for result the team are able to accurately
each with their own unique and the digital economy of the future. predict for the first time, using three-
unpredictable atomic-scale variations, “Since their invention in 1947, they dimensional numerical simulations, how
will perform within a circuit. have been getting smaller and smaller billions of microscopically different
The simulations will help tackle the so that today we can place billions of transistors will perform in future
problem of ‘statistical variability’ within transistors onto one small sliver of computer chips. The 3D simulations
transistors which is a major obstacle in silicon.” provide the scientists with information
Transistors today have gate lengths on the statistical distribution of the
of 40 nanometres; by comparison a transistors characteristics helping to
SOITEC and
human hair is around 100,000 predict how many of the transistors in a
nanometres wide. However, the smaller silicon chip will work. This information
they become, the more atomic-scale allows the chip designers to design
CEA combine
imperfections and variations within each reliable chips out of variable and
14
transistor become a problem. Statistical unreliable transistors.
for 3D
variations between transistors mainly Results of the simulation of
www
occur due to the random number and unprecedented numbers of transistors
.eur
integration
position of discrete dopants – chemical will be presented at the International
oasiasemiconductor
spices introduced in the silicon of which Electron Devices Meeting in Baltimore
the microchips are made to form the in December. Complementary results
structure of the individual transistors. were also published in the October
THE SOITEC GROUP and CEA-Leti This statistical variability means that edition of leading electronics device
have announced plans to expand their circuits built from billions of transistors journal ‘IEEE Transaction on Electron
collaboration on wafer-to-wafer 3D with individually-unique properties may Devices’.
.com
integration by offering customers a not perform as well as expected, Prof Asenov added: “The
joint, comprehensive industrial despite being manufactured in an NanoCMOS project has helped not only
solution. The global offer envisioned identical way. Prof Asenov said: “If we to understand, for the first time,
square4
Issue VIII 2009
by the long-term partners begins with are to continue to shrink the size of intimate details of statistical variability,
process customization for prototype transistors in order to develop ever but also to develop enhanced
demonstration and will include more powerful circuits, we need algorithms that will allow accurate
licensing, both in 200mm and 300mm. fundamentally new approaches to prediction of statistical variability with
3D-level integration allows circuit and system design that can take greatly reduced computational efforts.
stacking integrated circuits and account of the statistical variability. “This will be a great benefit, not
connecting them vertically. The “Up until now, Moore’s Law, the only to the major semiconductor
technology enables increased prediction made in 1965 by Intel co- manufacturers around the world, but
performance, smaller form factors, and founder Gordon Moore that transistor also to the vibrant UK chip design
reduced power consumption, while dimensions will scale continuously and industry that is facing the increasing
lowering the costs of next-generation the number of transistors that could be challenges of the modern nano-CMOS
electronic devices. Potential markets placed on a microchip would double technology and design.”
and applications include image every two years, has been the driving The NanoCMS grid computing
sensors, logic on logic, memory on force of the chip manufacturing and technology was developed by the
memory, sensors on logic, memory on design industry, but the days of ‘happy National e-Science Centre at the
logic and new heterogeneous scaling’ are over.” Universities of Glasgow and Edinburgh
solutions such as MEMS on logic and However, Prof Asen Asenov and his and the e-science North West Centre at
photonics on logic. team have applied grid computing Manchester University.
Page 1  |  Page 2  |  Page 3  |  Page 4  |  Page 5  |  Page 6  |  Page 7  |  Page 8  |  Page 9  |  Page 10  |  Page 11  |  Page 12  |  Page 13  |  Page 14  |  Page 15  |  Page 16  |  Page 17  |  Page 18  |  Page 19  |  Page 20  |  Page 21  |  Page 22  |  Page 23  |  Page 24  |  Page 25  |  Page 26  |  Page 27  |  Page 28  |  Page 29  |  Page 30  |  Page 31  |  Page 32  |  Page 33  |  Page 34  |  Page 35  |  Page 36  |  Page 37  |  Page 38  |  Page 39  |  Page 40  |  Page 41  |  Page 42  |  Page 43  |  Page 44