Research News
Maskless lithography boost
TSMC and CEA-Leti have signed an effective lithography and the for the industry. A maskless approach
agreement in which TSMC will join the development of maskless lithography is can offer flexibility and gain in cost of
new industrial program IMAGINE, led one of the potential solutions. We have ownership. Together with MAPPER, we
by CEA-Leti, on maskless lithography already announced the joint steps with see a route towards industrial
for IC manufacturing. Intended to Mapper to explore multiple e-beam throughput,” said Leti’s CEO, Laurent
operate for three years, this program lithography for IC manufacturing at 22 Malier. “Having TSMC on board the
allows companies to assess a maskless nanometer node and beyond,” said IMAGINE program is pivotal and will
lithography infrastructure for IC TSMC’s VP of R&D, Jack Sun. “By strengthen the assessment towards
manufacturing and use MAPPER joining the IMAGINE program at CEA- manufacturing. It shows the
technology as a solution towards high Leti, we intend to federate the commitment in the technology from the
throughput. It covers a global approach, semiconductor industry around this industry and will take maskless
including tool assessment, patterning technology and accelerate its lithography to the next step in the
and process integration, data handling, development and introduction for IC development that is required to make it
prototyping and cost analysis. manufacturing.” a viable solution for 22 nm
Issue V 2009
“TSMC is always pushing for cost “Lithography is a major challenge manufacturing.”
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Boost for EUV reality
JV for 3D IC
EV Group (EVG) has announced a joint
ASML and Cymer have announced the effort with Applied Materials to develop
shipment of the world’s first fully wafer bonding processes for the
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integrated laser-produced plasma (LPP) manufacture of through silicon vias
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Extreme Ultraviolet (EUV) lithography (TSVs) in three-dimensional integrated
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source to ASML. Cymer’s EUV source, circuit (3D IC) packaging applications.
the first of a multi-unit purchase The two will be working as members of
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agreement between the two the EMC-3D Semiconductor 3D
companies, is currently being installed Equipment and Materials Consortium.
at ASML’s Veldhoven headquarters EVG and Applied will work
where it will support integration and together to address issues by bonding
testing of EUV lithography scanners. production reality for chip makers temporary carrier wafers to device
Together with this shipment, Cymer worldwide,” added Martin van den wafers prior to thinning. The carriers will
announces achieving a record milestone Brink, executive vice president of support the ultra-thin device wafers
of 75 watts of EUV lithography Products and Technology at ASML. during subsequent process steps and
exposure power (full die exposure) and An LPP EUV lithography source, can be removed afterwards.
expects to scale to 100 watts exposure which produces “light” with 13.5 nm They will explore the use of silicon
power within the current quarter, wavelength (invisible to the human eye), and glass carrier wafers to determine
enabling scanner throughput of 60 represents a shift from today’s DUV substrate stability using EVG’s wafer
silicon wafers (300 mm/12 inch) per excimer sources. In an LPP EUV source, bonding and thin wafer handling and
hour which is required for volume microscopic droplets of molten tin are Applied’s advanced etch, CVD, PVD
manufacturing with ASML’s EUV fired through a vacuum chamber and and CMP process systems. The goal of
technology. First shipments of individually tracked and vaporized by a this effort is to yield baseline processes
production-capable EUV scanners from pulsed high power infrared laser, as and recommendations for the use of
ASML are planned a year from now. The frequently as 50,000 times per second, carrier mounted wafers throughout the
source concept will be capable of creating a high temperature tin plasma individual process steps offered by both
scaling over time to performance levels point source which radiates 13.5 nm parties. Results will be shared with
consistent with exposing more than 100 wavelength light. A large EUV mirror EMC-3D member companies.
wafers per hour when fully integrated collects and directs this light into the “We are excited to collaborate with
into ASML scanners. scanner where it is patterned by a an industry leader like Applied,” said
“Our team has worked hard to ship photomask and projected using a Markus Wimplinger, Corporate
the industry’s first LPP EUV lithography complex set of image reduction mirrors Technology Development and IP
source while achieving new levels of onto a light-sensitive silicon wafer, Director at EV Group “As a co-founder
EUV power,” said Bob Akins, chief transferring the pattern onto the wafer. of EMC-3D, EVG is committed to the
executive officer of Cymer. ASML has received orders for five consortium’s mission to develop cost-
“Cymer and ASML are committed EUV lithographic systems from memory effective and manufacturable TSVs for
to bringing EUV lithography to and logic customers for 2010. advanced semiconductors.
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