Introduction to microsectioning printed circuit boards
1. scratches are at a minimum. If there is avoid rounding of the outer plated edge. hole conditioning, electroless failure,
any evidence of voids or lack of resin Thoroughly rinse the sample and dry with resin state etc. Any degree of voiding
just before breaking through the hole a soft tissue or cloth. should be investigated as it will not
wall consider adding some more potting improve by itself.
compound and curing. This avoids State of the polished sample 10. Print, plate and etch voids. Generally
damage to what may be the only sample For photomicrography and critical evalu- due to surface contamination such as
being examined. This is very true on ation of such attributes as intermetallics resist residues preventing plating of the
small micro vias and holes plugged with a much higher degree of finish will be etch resist finish e.g. tin lead, tin, nickel
solder mask. It is, however, better to required than for routine plating thickness gold.
prick the mask before potting and add- measurements. The finish should be of 11. Barrel cracks as a result of thermal-
ing the epoxy. such a degree that the person looking at shock. Caused by “z” expansion of the
the sample can draw the right conclusions. base material exceeding the expansion
polishing It will be found that the results of a highly rate of the copper. It can be a ductil-
Using a cloth impregnated with diamond finished microsection viewed by a lesser ex- ity issue with the copper, the laminate
paste on a rotary wheel, 5 and 2.5 µm perienced operator will equate with results construction which is all exaggerated
pastes will give suitable final finish. When found by highly trained operator looking at by the higher temperatures of lead-free
not in use, the cloth shall be kept covered a lesser finished sample. assembly.
to prevent dust contamination. The polish- 12. Corner cracks as 11.
ing stage should be kept to a minimum to etching the sample 13. Misregistration of inner layer lands.
The etch selected should provide the May be due to inaccurate printing,
clearest possible contrast between deposits. laminate shift, artwork, drill program
The etch removes any slight traces of metal error, etc.
spread over the surfaces during polishing. 14. Material defects. May be purchased
With the use of SEM as opposed to optical material defect or pre-preg fault or poor
inspection etching may not be required. handling.
Today with full build copper and no elec- 15. Severe back etch. Caused by excessive
troless it can be difficult to show up the time in solution.
different copper layers. 16. Preferential resin attack during de-
Preliminary examination of the micro- smearing. Caused by incorrect solution
section prior to recording of results: make up or with plasma operation
excessive time.
1. Ensure holes if sectioned are, as near as
17. Pad lifting was originally seen during
possible, cut halfway through. Under
Figure 4. Blind via holes are an increasing chal-
the introduction of multilayer boards
or over grinding will give false plating
lenge to section correctly and then identify the root
with high z expansion; with lead-free
thickness results. (Plating will appear
cause of the failure, assembly or board fabrication.
soldering it will be seen again.
thicker than it really is.)
2. Ensure the hole sample has been Many of the photographs come from the
ground at 90˚ to the surface. “Printed Circuit Board Photo Album CD-
3. Check for resin shrinkage and separa- ROM” available to assist companies with
tion between sample and encapsulant. their training and inspection documenta-
4. Ensure sample has not been squashed. tion. The CD is available from the IPC.
This normally happens due to insuffi- This text was originally edited from ma-
cient resin being used or poor removal. terial produced for training courses run for
5. Check for deep scratches which may Institute of Circuit Technology (ICT). The
give the appearance of voids. The tell ICT training workshops were originally
tale sign is that the scratch will be presented by many of the well known engi-
evident in the resin as well as on the neers working in the PCB industry in the
sample. UK. A workshop covering “Printed Board
6. Ensure the sample was not damaged Inspection & Quality Control” is currently
during removal. conducted by the author for information
Figure 5. Voids in plating as a result of poor
7. Plating thickness. Results to plating bob@bobwillis.co.uk.
drilling.
shop and chemist. At least three read-
ings should be taken per finish i.e. both Bob Willis is a process engineer providing
surfaces and the hole. These readings engineering support in conventional and surface
plus the hole size and board thickness mount assembly processes. He runs produc-
allow the results to be compared from tion lines for suppliers at exhibitions and also
day to day in manufacture and thus provides seminar and workshops worldwide.
show up any plating deficiencies. Bob has one of the largest collections of training
8. Nailheading or drill burrs. Various videos, interactive CD-ROMs and training
causes for this defect. A few are drill material in the industry. Bob will be presenting
condition, feed and speed, resin cure, Master Classes at APEX in Las Vegas, he will
backing material not flat. Not usually also be presenting classes at SMT Nuremberg in
detrimental unless accompanied with Germany for those engineers visiting the show.
resin smear which can cause high resis- For further information on how Bob may be
Figure 6. Pad lifting was originally seen during the tance connections or even open circuits. able to support your staff contact him via his
introduction of multilayer boards with high z expan- 9. T.H.P. void. Due to many variables, web site www.ASKbobwillis.com
sion; with lead-free soldering it will be seen again.
some of which are damaged drills, poor
6 – Global SMT & Packaging – November 2008 www.globalsmt.net
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