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Wafer level packaging and the third dimension
Joe Fjelstad
Wafer level packaging
and the third dimension
Depending on how liberal one is in their for use in wafer-level-packaged camera of greatest interest. TVS technologies
definition of what a wafer level package modules in its novel and award winning are generally viewed as key to achieving
is, the technology is either entering its Optimil™ package. The technology is next generation density after the road
second, third or perhaps even its fourth or now being used to create the smallest ends for Moore’s Law by simply stacking
fifth decade of use. This is because of IBM’s camera yet devised. wafers, but the interest goes beyond in that
early flip chip efforts, which go back to the In the years that have followed TSV will allow for the assembly of mixed
1960s, are virtually indistinguishable from development of the early solutions, there IC technologies. In such constructions,
many devices that now claim to be wafer has been a flood of activity in pursuit selected wafers could be diced and
level packages. The more recent date can of the ideal wafer level package. Wafer their individual die then mounted and
be reasonably well marked by the work level packages are, in fact, a rapidly interconnected on a different wafer.
performed at the company M-Pulse (later growing area for IC packaging technology. The assembly can then be packaged for
re-christened Chip Scale, Inc) in San Jose, Moreover, while wafer level packaging mounting and use on and integration
CA, in the 1989–1990 time frame, where was once considered only suitable for few into a next level silicon assembly. This
and when wafer level packaging was a
defined objective for the creation of small
discrete active devices such as diodes and
“While there are a number of process
other few I/O components.
The package structure was created
variations for making the vias,
by selective etching of the silicon wafer
from the back side and then a patterning
application opportunities are most
and plating of metals resulting in a
wrap-around-the-edge interconnection
termination on the chip. The method
compelling and of greatest interest.”
resulted in a surface-mountable device that
was near chip size. The technique, then I/O devices, the technology is actually latter focus for what is being called “More
trade named MicroSMT, was well suited fairly commonly used for high I/O devices, than more than Moore” by researchers at
to few I/O applications and provided high such as microprocessors, where flip chip Georgia Tech’s Packaging Research Center
performance devices. One drawback of the sub-packages are mounted on high density as a clever play on the “More than Moore
early method was that an extra wide space substrates. Wafer level packaging is rather than More of Moore” rallying cry of
was required between chips on the wafer. migrating into mid-pin-count ranges as 3D packaging technology that preceded it.
Given the cost of semiconductor chip well, such as is used for memory devices. In summary, the edges of the envelope
processing (which, for reference, can be as At the same time, IC packing focus has of IC packaging technology continue
high as one billion dollars an acre when been shifting to the third dimension and to be pressed out by a combination of
finished), the lost opportunity to create a wide range of chip and package stacking necessity, logic and creative engineering.
more semiconductors made it a concern concepts. These concepts also have deep Examination of the potential of the
for more complex ICs. That said, Chip roots that reach back to at least the 1980s, third dimension is now in full swing as
Scale, Inc’s engineering team also had the but now with much greater vigor. Up to we attempt to, with each new generation
insight and vision that the technology nine-high stacked chip assemblies have of product, offer more performance and
could be adapted to the creation of area been reported. It comes then with little more features at ever-lower costs. In
array interconnections on either side of surprise that there in a growing interest today’s economic environment of higher
the package, making it more suitable for in stacking wafers with interconnections energy costs and more expensive and
higher I/O application. It is a technique created by means of through silicon via energy intensive lead-free soldering
that was followed up on and adopted by the (TSV) technologies. requirements, it is not clear that the latter
company Shellcase in Israel (now owned by While there are a number of process objective will be met, but one can rest
Tessera Technologies, Inc, San Jose, CA) variations for making the vias, application assured that the march of technology will
and has been recently successfully adapted opportunities are most compelling and continue unabated.
4 – Global SMT & Packaging - August 2008 www.globalsmt.net
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